Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

Yewale, Shubhara; Gamad, Radheshyam

Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

Files

Design of Low Power and High Speed CMOS Comparator for AD Converter Application.pdf (1.32 MB)

Date

2012-04

Authors

Yewale, Shubhara

Gamad, Radheshyam

Publisher

Scientific Research Publishing

Abstract

This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.

Keywords

CMOS Comparato, Low Power, High Speed, Sigma-Delta ADC and Cadence

Citation

Wireless Engineering and Technology, 2012, 3, 90-95

URI

http://dx.doi.org/10.4236/wet.2012.32015
http://hdl.handle.net/123456789/1230

Collections

Computer Science & Communications

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